1. Field
The embodiments discussed herein are directed to a semiconductor device and a method for manufacturing the same.
2. Description of the Related Art
Recently, the market size of large-scale integration (LSI) for mobile devices has been rapidly expanding as the demand for mobile devices such as cellular phones increases. Most of the mobile devices are battery-driven, so that there is a limitation on long term use of the mobile devices. Accordingly, not only higher operation but also lower power consumption are desired for the semiconductor devices such as the above-described LSI.
There are various types of semiconductor devices to be mounted on such mobile devices. In particular, an SRAM (static random access memory) can be operated at a higher speed than other memory devices, and thereby widely used for system memories of mobile devices and the like. An SRAM is classified into a six-transistor-type, a three-transistor-type, and the like, according to a structure of a cell. Among these types, FIG. 1 shows an equivalent circuit of one cell of a six-transistor-type SRAM.
As shown in FIG. 1, this type of SRAM includes transfer transistors TRT1, and TRT2 and driver transistors TRD1 and TRD2, all of which are n-type MOS (metal oxide semiconductor) transistors. Furthermore, in addition to these transistors, two load transistors TRL1, and TRL2, which are p-type MOs transistors, are connected as shown in the figure, so that one cell of SRAM is made, which is driven between a power voltage VDD and a ground potential GND.
FIG. 2 is a plan view of this SRAM.
As shown in FIG. 2, this SRAM includes a silicon substrate 1 on which active regions 4 for the n-type MOS transistors and active regions 5 for p-type MOS transistors are formed, and further includes gate electrodes 2 formed on these active regions 4 and 5 with a gate insulating film interposed therebetween (not shown). Then, a plurality of conductive plugs 3 are formed on the active regions 4 and 5 and the gate electrodes 2 so as to obtain the equivalent circuit of FIG. 1 by electrically connecting them with a metal wiring which is not shown in the figure.
FIG. 3 is a view enabling a plan layout of the active regions 4 and 5 to be easily viewed by omitting the above-described gate electrodes 2 and conductive plugs 3.
As shown in the figure, the active regions 4 for the n-type MOS transistors are defined by first openings 6a of device isolation insulating films 6 formed on the silicon substrate 1. In addition, the active regions 5 for p-type MOS transistors are defined by second openings 6b of the device isolation insulating films 6.
Various plan layouts for the active regions 4 and 5 have been invented. In the example of FIG. 3, to cause an active region 4 for the n-type MOS transistor to be shared by plural cells, a plan layout thereof is stripe-shaped. Such an SRAM is referred to as a stripe-shaped SRAM, which was popularly adopted at the early period when the SRAM was available on the market. It was once considered that the stripe-shaped SRAM was not suitable for higher integration. However, it has been found out recently that this type of SRAM is rather advantageous in higher integration, so that attention has been given on the stripe-shaped SRAM again.
In contrast, FIG. 4 is a plan view of SRAM referred to as a bent-shaped type. The same reference numerals are given to the components described in FIG. 2. FIG. 5 is a view enabling a plan view of the active regions 4 and 5 to be easily viewed by omitting the gate electrodes 2 of FIG. 4.
As shown in FIG. 5, each of the active regions 4 for the n-type MOS transistors is shared by two upper and lower cells and is bent in each cell to be loop-shaped. Each of the active regions 4 for n-type transistors is bent, so that a cell size can be made smaller, thereby higher integration of SRAM can be made.
Note that technologies relating to the present application have been also disclosed in patent literatures 3 to 5.
Patent literature 1: Japanese Patent Application Laid-open Publication No. 2003-179166
Patent literature 2: Japanese Patent Application Laid-open Publication No. 2001-332634
Patent literature 3: Japanese Patent Application Laid-open Publication No. Hei 10-173073
Patent literature 4: Japanese Patent Application Laid-open Publication No. 2002-43441
Patent literature 5: Japanese Patent Application Laid-open Publication No. 2002-353340